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<title>UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS </title></head>
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<h1>UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 2E /r</p>
<p>UCOMISS xmm1, xmm2/m32</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr>
<tr>
<td>
<p>VEX.128.0F.WIG 2E /r</p>
<p>VUCOMISS xmm1, xmm2/m32</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr>
<tr>
<td>
<p>EVEX.LIG.0F.W0 2E /r</p>
<p>VUCOMISS xmm1, xmm2/m32{sae}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Compares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-dered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-dered result is returned if either source operand is a NaN (QNaN or SNaN).</p>
<p>Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.</p>
<p>The UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid opera-tion exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric excep-tion when a source operand is either a QNaN or SNaN.</p>
<p>The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
<p>Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
<p><strong>Operation</strong></p>
<p><strong>(V)UCOMISS (all versions)</strong></p>
<p>RESULT (cid:197)(cid:3)UnorderedCompare(DEST[31:0] &lt;&gt; SRC[31:0]) {</p>
<p>(* Set EFLAGS *) CASE (RESULT) OF</p>
<p>UNORDERED: ZF,PF,CF (cid:197) 111;</p>
<p>GREATER_THAN: ZF,PF,CF (cid:197) 000;</p>
<p>LESS_THAN: ZF,PF,CF (cid:197) 001;</p>
<p>EQUAL: ZF,PF,CF (cid:197) 100;</p>
<p>ESAC;</p>
<p>OF, AF, SF (cid:197) 0; }</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VUCOMISS</p>
<p>int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);</p>
<p>UCOMISS</p>
<p>int _mm_ucomieq_ss(__m128 a, __m128 b);</p>
<p>UCOMISS</p>
<p>int _mm_ucomilt_ss(__m128 a, __m128 b);</p>
<p>UCOMISS</p>
<p>int _mm_ucomile_ss(__m128 a, __m128 b);</p>
<p>UCOMISS</p>
<p>int _mm_ucomigt_ss(__m128 a, __m128 b);</p>
<p>UCOMISS</p>
<p>int _mm_ucomige_ss(__m128 a, __m128 b);</p>
<p>UCOMISS</p>
<p>int _mm_ucomineq_ss(__m128 a, __m128 b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid (if SNaN Operands), Denormal</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>VEX-encoded instructions, see Exceptions Type 3; additionally</td></tr>
<tr>
<td>If VEX.vvvv != 1111B.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3NF.</td></tr></table></body></html>